diff -up ./arch/x86/Kconfig.cpu.sse ./arch/x86/Kconfig.cpu
--- ./arch/x86/Kconfig.cpu.sse	2026-05-29 19:09:36.218889284 +0900
+++ ./arch/x86/Kconfig.cpu	2026-05-29 19:15:32.788966974 +0900
@@ -412,6 +412,21 @@ config CPU_EMU_FUCOMI
 
 	If you are not sure, say N.
 
+config CPU_EMU_SSE2
+	bool "SSE2 instruction emulation"
+	depends on X86_32 && CPU_EMU486
+	help
+	This attemps to emulate certain SSE2 codes by software.
+	This will allow programs compiled by -mfpmath=sse, which is now common for
+	.i686 distributions, to run on CPUs without SSE2.
+
+	WARNING: This only works with CPUs withOUT MMX. Since some SSE
+	instructions are interpreted as MMX instructions on non-SSE
+	processors, it is impossible to emulate them via #UD exception.
+	Practically only works on plain Pentuim P54C without MMX.
+
+	If you are not sure, say N.
+
 config CPU_PROC_EMULATED_OPS
 	bool "/proc/emulated_ops support"
 	depends on X86_32 && CPU_EMU486
diff -up ./arch/x86/include/asm/fpu/types.h.sse ./arch/x86/include/asm/fpu/types.h
--- ./arch/x86/include/asm/fpu/types.h.sse	2026-02-01 08:09:53.000000000 +0900
+++ ./arch/x86/include/asm/fpu/types.h	2026-05-29 19:15:32.789966977 +0900
@@ -442,6 +442,14 @@ struct fpu_state_perm {
 	unsigned int			__user_state_size;
 };
 
+#if defined(CONFIG_CPU_EMU_SSE2)
+/* Software emulated XMM registers */
+union xmm_t {
+	struct { u64 q[2]; } qw;
+	struct { s32 d[4]; } dw;
+};
+#endif
+
 /*
  * Highest level per task FPU state data structure that
  * contains the FPU register state plus various FPU
@@ -499,6 +507,15 @@ struct fpu {
 	 */
 	struct fpu_state_perm		guest_perm;
 
+#if defined(CONFIG_CPU_EMU_SSE2)
+	/*
+	 * @xmm:
+	 * Software emulated XMM registers
+	 * This does not belong here, but state->fsave is not always available
+	 */
+	union xmm_t xmm[8];	/* 8 XMM registers, 128bit */
+#endif
+
 	/*
 	 * @__fpstate:
 	 *